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24C02C
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
Name
A0
A1
A2
V SS
SDA
SCL
WP
V CC
PDIP
1
2
3
4
5
6
7
8
SOIC
1
2
3
4
5
6
7
8
TSSOP
1
2
3
4
5
6
7
8
DFN/TDFN
1
2
3
4
5
6
7
8
MSOP
1
2
3
4
5
6
7
8
Function
Address Pin A0
Address Pin A1
Address Pin A2
Ground
Serial Address/Data I/O
Serial Clock
Write-Protect Input
+4.5 V to 5.5 V Power Supply
2.1
SDA Serial Data
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal; therefore, the SDA bus requires a pull-
up resistor to V CC (typical 10 k Ω for 100 kHz, 2 k Ω for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.2
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
2.3
A0, A1, A2
The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.
Up to eight 24C02C devices may be connected to the
same bus by using different Chip Select bit combina-
tions. These inputs must be connected to either V CC or
V SS .
2.4
WP
This is the hardware write-protect pin. It must be tied to
V CC or V SS . If tied to Vcc, the hardware write protection
is enabled. If the WP pin is tied to V SS the hardware
write protection is disabled.
2.5
Noise Protection
The 24C02C employs a V CC threshold detector circuit
which disables the internal erase/write logic if the V CC
is below 3.8 volts at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
? 2008 Microchip Technology Inc.
DS21202J-page 5
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